Invention Grant
- Patent Title: Multiplication circuit and de/encryption circuit utilizing the same
- Patent Title (中): 乘法电路和使用其的去/加密电路
-
Application No.: US12057266Application Date: 2008-03-27
-
Publication No.: US08443032B2Publication Date: 2013-05-14
- Inventor: Chen Hsing Wang , Chieh Lin Chuang , Cheng Wen Wu
- Applicant: Chen Hsing Wang , Chieh Lin Chuang , Cheng Wen Wu
- Applicant Address: TW Hsinchu
- Assignee: National Tsing Hua University
- Current Assignee: National Tsing Hua University
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C.
- Agent Anthony King
- Main IPC: G06F7/52
- IPC: G06F7/52
Abstract:
A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.
Public/Granted literature
- US20090245505A1 MULTIPLICATION CIRCUIT AND DE/ENCRYPTION CIRCUIT UTILIZING THE SAME Public/Granted day:2009-10-01
Information query
