Invention Grant
- Patent Title: Control of clock gate cells during scan testing
- Patent Title (中): 在扫描测试期间控制时钟门单元
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Application No.: US13014921Application Date: 2011-01-27
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Publication No.: US08443246B1Publication Date: 2013-05-14
- Inventor: Darren Bertanzetti
- Applicant: Darren Bertanzetti
- Applicant Address: BM Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM Hamilton
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/02 ; G01R31/26 ; G06F11/00

Abstract:
A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
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