Invention Grant
- Patent Title: Rate-scalable, multistage quasi-cyclic LDPC coding
- Patent Title (中): 速率可缩放,多级准循环LDPC编码
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Application No.: US13039068Application Date: 2011-03-02
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Publication No.: US08443257B1Publication Date: 2013-05-14
- Inventor: Lingqi Zeng , Yu Kou , Kin Man Ng , Kwok W. Yeung
- Applicant: Lingqi Zeng , Yu Kou , Kin Man Ng , Kwok W. Yeung
- Applicant Address: US CA San Jose
- Assignee: SK hynix memory solutions inc.
- Current Assignee: SK hynix memory solutions inc.
- Current Assignee Address: US CA San Jose
- Agency: Van Pelt, Yi & James LLP
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the plurality of circulant vectors; the number of circulant vectors in the subset equals the integer multiplier.
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