Invention Grant
- Patent Title: Circuit design optimization
- Patent Title (中): 电路设计优化
-
Application No.: US12858522Application Date: 2010-08-18
-
Publication No.: US08443313B2Publication Date: 2013-05-14
- Inventor: Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
- Applicant: Samuel I. Ward , Kevin F. Reick , Bryan J. Robbins , Thomas E. Rosser , Robert J. Shadowen
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: The Caldwell Firm, LLC
- Agent Patrick E. Caldwell, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool.
Public/Granted literature
- US20120047476A1 CIRCUIT DESIGN OPTIMIZATION Public/Granted day:2012-02-23
Information query