Invention Grant
- Patent Title: Transformation of IC designs for formal verification
- Patent Title (中): IC设计转型正式验证
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Application No.: US12511987Application Date: 2009-07-29
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Publication No.: US08443317B2Publication Date: 2013-05-14
- Inventor: Muzaffer Hiraoglu , Peter Wilhelm Josef Zepter
- Applicant: Muzaffer Hiraoglu , Peter Wilhelm Josef Zepter
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A non-transitory computer readable storage media, a computer-implemented method and apparatus for electronic design automation are disclosed. A reference integrated circuit (IC) design and a remitted IC design are received. Instances of cells of the reference IC design and the retimed IC designed are replaced with replacement circuits based on a description of moves of retiming associated with the reference IC design and the synthesized IC design. A comparison of the reference IC design and the retimed IC designed is performed to determine whether the retimed IC design is equivalent to the transformed IC design.
Public/Granted literature
- US20090293028A1 TRANSFORMATION OF IC DESIGNS FOR FORMAL VERIFICATION Public/Granted day:2009-11-26
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