Invention Grant
- Patent Title: Method and apparatus for manufacturing a multi layer chip capacitor
- Patent Title (中): 制造多层片状电容器的方法和装置
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Application No.: US13079573Application Date: 2011-04-04
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Publication No.: US08443498B2Publication Date: 2013-05-21
- Inventor: Jae-Ho Ha
- Applicant: Jae-Ho Ha
- Applicant Address: KR Daegu
- Assignee: Sehyang Industrial Co., Ltd.
- Current Assignee: Sehyang Industrial Co., Ltd.
- Current Assignee Address: KR Daegu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: KR10-2005-0053559 20050621; KR10-2006-0055074 20060619
- Main IPC: H01G7/00
- IPC: H01G7/00

Abstract:
The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.
Public/Granted literature
- US20110181999A1 MULTI LAYER CHIP CAPACITOR, AND METHOD AND APPARATUS FOR MANUFACTURING THE SAME Public/Granted day:2011-07-28
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