Invention Grant
US08445974B2 Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same
有权
包括倾斜阈值电压调节材料层的不对称FET及其制造方法
- Patent Title: Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same
- Patent Title (中): 包括倾斜阈值电压调节材料层的不对称FET及其制造方法
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Application No.: US12683602Application Date: 2010-01-07
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Publication No.: US08445974B2Publication Date: 2013-05-21
- Inventor: Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
- Applicant: Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent H. Daniel Schnurmann
- Main IPC: H01L21/02
- IPC: H01L21/02
Abstract:
A semiconductor structure is provided that includes at least one asymmetric gate stack located on a surface of a semiconductor structure. The at least one asymmetric gate stack includes, from bottom to top, a high k gate dielectric, a sloped threshold voltage adjusting material layer and a gate conductor. A method of forming such a semiconductor structure is also provided in which a line of sight deposition process is used in forming the sloped threshold voltage adjusting material layer in which the deposition is tilted within respect to a horizontal surface of a semiconductor structure.
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