Invention Grant
- Patent Title: Semiconductor device having a lower-layer line
- Patent Title (中): 具有下层线路的半导体器件
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Application No.: US12385839Application Date: 2009-04-21
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Publication No.: US08445987B2Publication Date: 2013-05-21
- Inventor: Tetsuya Katou
- Applicant: Tetsuya Katou
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-137844 20080527
- Main IPC: H01L21/70
- IPC: H01L21/70

Abstract:
A semiconductor device includes a semiconductor substrate, a first lower-layer line for supplying power to a transistor formed on the semiconductor substrate, a first interlayer line which is connected to the first lower-layer line, and an allowable current of which is larger than that of the first lower-layer line; and an upper-layer line which is provided above the first interlayer line and receives power input from outside. The first interlayer line is connected to the upper-layer line through a switch circuit formed on the semiconductor substrate.
Public/Granted literature
- US20090295463A1 SEMICONDUCTOR DEVICE Public/Granted day:2009-12-03
Information query
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