Invention Grant
- Patent Title: Input interface circuit
- Patent Title (中): 输入接口电路
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Application No.: US12801482Application Date: 2010-06-10
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Publication No.: US08446196B2Publication Date: 2013-05-21
- Inventor: Kazuo Watanabe
- Applicant: Kazuo Watanabe
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2009-190102 20090819
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through the clock tree circuit and is supplied to the latch circuit in response to a comparison result between the clock and an output from a replica delay circuit which is replicated from the clock.
Public/Granted literature
- US20110043262A1 Input interface circuit Public/Granted day:2011-02-24
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