A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching between a fast clock signal input to the counter and a slow clock input to the counter. The counter is always on and increases its count by an appropriate rational number of counts representing fast clock cycles for every cycle of the fast clock while in a fast clock mode, and by an appropriate rational number of fast clock periods for every cycle of the slow clock signal while in a slow clock mode.