A shift frequency demultiplier with automatic reset function is N-frequency demultiplication (N>2) and includes N-1 registers connected with each other and defined from a first register to an (N-1)th register. Each of the registers has an input end, an output end, a reset end and a clock end. For the registers from the first register to the (N-2)th register, the output end of every register is connected with the input end of a next register adjacent thereto, the output end of the (N-1)th register is connected with the input end of the first register by a reverser. The reset end of the (N-1)th register is connected with a system reset signal end. The system reset signal end logically multiplied by the output end of the (N-1)th register is connected with the reset ends of the registers from the first register to the (N-2)th register.