Invention Grant
US08447798B2 Look up table (LUT) structure supporting exclusive or (XOR) circuitry configured to allow for generation of a result using quaternary adders
有权
查找表（LUT）结构，支持独占或（XOR）电路，配置为允许使用四进制加法器生成结果
- Patent Title: Look up table (LUT) structure supporting exclusive or (XOR) circuitry configured to allow for generation of a result using quaternary adders
- Patent Title (中): 查找表（LUT）结构，支持独占或（XOR）电路，配置为允许使用四进制加法器生成结果
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Application No.: US12732104Application Date: 2010-03-25
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Publication No.: US08447798B2Publication Date: 2013-05-21
- Inventor: Martin Langhammer
- Applicant: Martin Langhammer
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: G06F7/42
- IPC: G06F7/42
Abstract:
A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.
Public/Granted literature
- US20110238718A1 LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS Public/Granted day:2011-09-29
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