Invention Grant
- Patent Title: Post timing layout modification for performance
- Patent Title (中): 发布时序布局修改的性能
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Application No.: US13236977Application Date: 2011-09-20
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Publication No.: US08448124B2Publication Date: 2013-05-21
- Inventor: Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
- Applicant: Uwe Fassnacht , Veit Gernhoefer , Michael S. Gray , Joachim Keinert
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen R. Tkacs; Stephen J. Walder, Jr.; Matthew B. Talpis
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
A mechanism is provided for post timing layout modification for performance. The mechanism selectively applies layout modification based on timing analysis at the path level. The mechanism applies stress only to transistors that are in a setup critical path without applying stress to transistors in hold critical paths. The mechanism may use a method to apply stress to improve performance of a transistor in a setup critical path, as long as the stress does not also improve performance of a neighboring transistor in a hold critical path. In some instances, the mechanism may apply stress to improve performance of a transistor in a setup critical path while simultaneously degrading performance of a transistor in a hold critical path.
Public/Granted literature
- US20130074025A1 POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE Public/Granted day:2013-03-21
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