Invention Grant
- Patent Title: 3D multiple die stacking
- Patent Title (中): 3D多芯片堆叠
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Application No.: US12561618Application Date: 2009-09-17
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Publication No.: US08455270B2Publication Date: 2013-06-04
- Inventor: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer
- Applicant: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Catherine Ivers; Ira D. Blecker
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L21/66
Abstract:
A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.
Public/Granted literature
- US20110065214A1 3D MULTIPLE DIE STACKING Public/Granted day:2011-03-17
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