Invention Grant
US08455300B2 Integrated circuit package system with embedded die superstructure and method of manufacture thereof
有权
具有嵌入式模具上层结构的集成电路封装系统及其制造方法
- Patent Title: Integrated circuit package system with embedded die superstructure and method of manufacture thereof
- Patent Title (中): 具有嵌入式模具上层结构的集成电路封装系统及其制造方法
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Application No.: US12787216Application Date: 2010-05-25
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Publication No.: US08455300B2Publication Date: 2013-06-04
- Inventor: HeeJo Chi , NamJu Cho , ChanHoon Ko
- Applicant: HeeJo Chi , NamJu Cho , ChanHoon Ko
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Agent John Yang
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/06 ; H01L23/02

Abstract:
A method of manufacture of an integrated circuit package system includes: providing a through-silicon-via die having conductive vias therethrough; forming a first redistribution layer on a bottom of the through-silicon-via die coupled to the conductive vias; forming a second redistribution layer on the top of the through-silicon-via die coupled to the conductive vias; fabricating an embedded die superstructure on the second redistribution layer including: mounting an integrated circuit die to the second redistribution layer, forming a core material layer on the second redistribution layer to be coplanar with the integrated circuit die, forming a first build-up layer, having contact links coupled to the integrated circuit die, on the core material layer, and coupling component interconnect pads to the contact links; and forming system interconnects on the first redistribution layer for coupling the through-silicon-via die, the integrated circuit die, the component interconnect pads, or a combination thereof.
Public/Granted literature
- US20110291283A1 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EMBEDDED DIE SUPERSTRUCTURE AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2011-12-01
Information query
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