Invention Grant
- Patent Title: Methods of forming voltage limiting devices
- Patent Title (中): 形成电压限制装置的方法
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Application No.: US13480924Application Date: 2012-05-25
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Publication No.: US08455306B2Publication Date: 2013-06-04
- Inventor: Amaury Gendron , Chai Ean Gill , Rouying Zhan
- Applicant: Amaury Gendron , Chai Ean Gill , Rouying Zhan
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Sherry W. Schumm
- Main IPC: H01L21/332
- IPC: H01L21/332 ; H01L21/00 ; H01L27/02

Abstract:
Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.
Public/Granted literature
- US20120231587A1 METHODS OF FORMING VOLTAGE LIMITING DEVICES Public/Granted day:2012-09-13
Information query
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