Invention Grant
US08455347B1 Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types 有权
用于为多种封装类型配置集成电路的结构,架构,系统,方法,算法和软件

  • Patent Title: Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types
  • Patent Title (中): 用于为多种封装类型配置集成电路的结构,架构,系统,方法,算法和软件
  • Application No.: US13154180
    Application Date: 2011-06-06
  • Publication No.: US08455347B1
    Publication Date: 2013-06-04
  • Inventor: Tyson LeistikoHuahung Kao
  • Applicant: Tyson LeistikoHuahung Kao
  • Applicant Address: BM Hamilton
  • Assignee: Marvell International Ltd.
  • Current Assignee: Marvell International Ltd.
  • Current Assignee Address: BM Hamilton
  • Main IPC: H01L21/4763
  • IPC: H01L21/4763
Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types
Abstract:
Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting one of a plurality of packaging types for an integrated circuit. The structure generally comprises a bump pad, a plurality of bond pads configured for independent electrical connection to the bump pad, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the bump pad. The software is generally configured to place and route components of such a structure. The method of configuring generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. The method of selecting generally comprises the uppermost metal layer-forming step, and forming either (i) a wire bond to at least one of the bond pads, or (ii) a bumping metal configured to electrically connect at least one of the bond pads to the bump pad. The present invention advantageously provides reduced manufacturing costs and reduced inventory management issues by enabling one device to be manufactured at a wafer level for a plurality of different packaging options, thereby enabling packaging decisions to be made at a later time in the manufacturing process.
Information query
IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件;其他类目中不包括的电固体器件(使用半导体器件的测量入G01;一般电阻器入H01C;磁体、电感器、变压器入H01F;一般电容器入H01G;电解型器件入H01G9/00;电池组、蓄电池入H01M;波导管、谐振器或波导型线路入H01P;线路连接器、汇流器入H01R;受激发射器件入H01S;机电谐振器入H03H;扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R;一般电光源入H05B;印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K;在具有特殊应用的电路中使用的半导体器件见应用相关的小类)
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02 .半导体器件或其部件的制造或处理
H01L21/04 ..至少具有一个跃变势垒或表面势垒的器件,例如PN结、耗尽层、载体集结层
H01L21/34 ...具有H01L21/06,H01L21/16及H01L21/18各组不包含的或有或无杂质,例如掺杂材料的半导体的器件
H01L21/46 ....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的(在半导体材料上制作电极的入H01L21/44)
H01L21/461 .....改变半导体材料的表面物理特性或形状的,例如腐蚀、抛光、切割
H01L21/4763 ......非绝缘层的沉积,例如绝缘层上的导电层、电阻层;这些层的后处理(电极的制造入H01L21/28)
Patent Agency Ranking
0/0