Invention Grant
US08455357B2 Method of plating through wafer vias in a wafer for 3D packaging
有权
通过晶片通孔在3D封装中进行电镀的方法
- Patent Title: Method of plating through wafer vias in a wafer for 3D packaging
- Patent Title (中): 通过晶片通孔在3D封装中进行电镀的方法
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Application No.: US13120988Application Date: 2009-09-28
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Publication No.: US08455357B2Publication Date: 2013-06-04
- Inventor: Willem Frederik Adrianus Besling , Freddy Roozeboom , Yann Pierre Roger Lamy
- Applicant: Willem Frederik Adrianus Besling , Freddy Roozeboom , Yann Pierre Roger Lamy
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: McClure, Qualey & Rodack, LLP
- Priority: EP08166357 20081010
- International Application: PCT/IB2009/054233 WO 20090928
- International Announcement: WO2010/041165 WO 20100415
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/4763 ; H01L21/311 ; H01L29/40 ; H01L23/053 ; H01L23/12 ; H01L23/48 ; H01L23/52
Abstract:
A method of plating via hole in a substrate includes providing a substrate having a first side and a second side and a plurality of through substrate via holes; depositing a first seed layer on the first side of the substrate; applying a foil on the first seed layer of the substrate closing the first ends of the plurality of via holes; electro-chemical plating of the second side of the substrate; and removing the foil.
Public/Granted literature
- US20120133047A1 Method of Plating Through Wafer Vias in a Wafer for 3D Packaging Public/Granted day:2012-05-31
Information query
IPC分类:
