Invention Grant
- Patent Title: Method of fabricating wiring board and method of fabricating semiconductor device
- Patent Title (中): 制造布线板的方法和制造半导体器件的方法
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Application No.: US13196129Application Date: 2011-08-02
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Publication No.: US08455770B2Publication Date: 2013-06-04
- Inventor: Junichi Nakamura , Yuji Kobayashi
- Applicant: Junichi Nakamura , Yuji Kobayashi
- Applicant Address: JP Nagano-Shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-Shi
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2005-159993 20050531; JP2006-014199 20060123
- Main IPC: H05K1/11
- IPC: H05K1/11

Abstract:
A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.
Public/Granted literature
- US20110286189A1 METHOD OF FABRICATING WIRING BOARD AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2011-11-24
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