Invention Grant
US08455923B2 Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
失效
嵌入式NOR闪存过程与NAND单元和真正的逻辑兼容低电压器件
- Patent Title: Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device
- Patent Title (中): 嵌入式NOR闪存过程与NAND单元和真正的逻辑兼容低电压器件
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Application No.: US13135220Application Date: 2011-06-29
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Publication No.: US08455923B2Publication Date: 2013-06-04
- Inventor: Peter Wung Lee , Han-Rei Ma , Fu-Chang Hsu
- Applicant: Peter Wung Lee , Han-Rei Ma , Fu-Chang Hsu
- Applicant Address: US CA San Jose
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: H01L27/118
- IPC: H01L27/118

Abstract:
An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.
Public/Granted literature
- US20120001233A1 Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device Public/Granted day:2012-01-05
Information query
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