Invention Grant
US08455937B2 Nonvolatile semiconductor memory device in which decrease in coupling ratio of memory cells is suppressed
失效
非易失性半导体存储器件，其中抑制了存储器单元的耦合比的降低
- Patent Title: Nonvolatile semiconductor memory device in which decrease in coupling ratio of memory cells is suppressed
- Patent Title (中): 非易失性半导体存储器件，其中抑制了存储器单元的耦合比的降低
-
Application No.: US12507416Application Date: 2009-07-22
-
Publication No.: US08455937B2Publication Date: 2013-06-04
- Inventor: Toshitake Yaegashi
- Applicant: Toshitake Yaegashi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-023850 20060131
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/788
Abstract:
A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer.
Public/Granted literature
Information query
IPC分类:
