Invention Grant
- Patent Title: Power MISFET semiconductor device
- Patent Title (中): 功率MISFET半导体器件
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Application No.: US13181816Application Date: 2011-07-13
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Publication No.: US08455943B2Publication Date: 2013-06-04
- Inventor: Yoshito Nakazawa , Hitoshi Matsuura
- Applicant: Yoshito Nakazawa , Hitoshi Matsuura
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Mattingly & Malur, PC
- Priority: JP2008-101242 20080409
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/40

Abstract:
Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.
Public/Granted literature
- US20110266617A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Public/Granted day:2011-11-03
Information query
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