Invention Grant
US08455982B2 Overlay mark enhancement feature 有权
叠加标记增强功能

Overlay mark enhancement feature
Abstract:
An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.
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