Invention Grant
- Patent Title: Overlay mark enhancement feature
- Patent Title (中): 叠加标记增强功能
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Application No.: US13408618Application Date: 2012-02-29
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Publication No.: US08455982B2Publication Date: 2013-06-04
- Inventor: Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
- Applicant: Meng-Wei Chen , Chi-Chuang Lee , Chung-Hsien Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/06
- IPC: H01L29/06

Abstract:
An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.
Public/Granted literature
- US20120153441A1 OVERLAY MARK ENHANCEMENT FEATURE Public/Granted day:2012-06-21
Information query
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