Invention Grant
- Patent Title: Method for reducing chip warpage
- Patent Title (中): 降低芯片翘曲的方法
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Application No.: US13240540Application Date: 2011-09-22
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Publication No.: US08455999B2Publication Date: 2013-06-04
- Inventor: Ting-Hau Wu , Chun-Ren Cheng , Jiou-Kang Lee , Shang-Ying Tsai , Jung-Huei Peng
- Applicant: Ting-Hau Wu , Chun-Ren Cheng , Jiou-Kang Lee , Shang-Ying Tsai , Jung-Huei Peng
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/34
- IPC: H01L23/34

Abstract:
A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.
Public/Granted literature
- US20120007220A1 Method for Reducing Chip Warpage Public/Granted day:2012-01-12
Information query
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