Invention Grant
- Patent Title: Semiconductor package and method of manufacturing the same
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US12906377Application Date: 2010-10-18
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Publication No.: US08456020B2Publication Date: 2013-06-04
- Inventor: Yoichiro Kurita , Masaya Kawano
- Applicant: Yoichiro Kurita , Masaya Kawano
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2009-239676 20091016
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40

Abstract:
A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.
Public/Granted literature
- US20110089561A1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2011-04-21
Information query
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