Invention Grant
- Patent Title: Semiconductor device having a pad-disposition restriction area
- Patent Title (中): 具有垫配置限制区域的半导体器件
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Application No.: US13489215Application Date: 2012-06-05
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Publication No.: US08456024B2Publication Date: 2013-06-04
- Inventor: Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
- Applicant: Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2003-087824 20030327
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
Public/Granted literature
- US20120241970A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-09-27
Information query
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