Invention Grant
- Patent Title: Semiconductor chip having staggered arrangement of bonding pads
- Patent Title (中): 半导体芯片具有交错布置的焊盘
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Application No.: US13220860Application Date: 2011-08-30
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Publication No.: US08456025B2Publication Date: 2013-06-04
- Inventor: Kenji Yokoyama
- Applicant: Kenji Yokoyama
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2009-140880 20090612
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A semiconductor integrated circuit device includes a semiconductor chip including input/output cells, pads formed on a surface of the semiconductor chip, and interconnects formed on the surface of the semiconductor chip to electrically connect at least some of the plurality of input/output cells and at least some of the plurality of pads. A first plurality of the pads located in a center portion of the semiconductor chip are arranged in a rectangular dot grid pattern, and a second plurality of the pads located in at least one of four corner portions of the semiconductor chip are arranged in a staggered dot pattern.
Public/Granted literature
- US20110309515A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR DESIGNING THE SAME Public/Granted day:2011-12-22
Information query
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