Invention Grant
US08456025B2 Semiconductor chip having staggered arrangement of bonding pads 有权
半导体芯片具有交错布置的焊盘

Semiconductor chip having staggered arrangement of bonding pads
Abstract:
A semiconductor integrated circuit device includes a semiconductor chip including input/output cells, pads formed on a surface of the semiconductor chip, and interconnects formed on the surface of the semiconductor chip to electrically connect at least some of the plurality of input/output cells and at least some of the plurality of pads. A first plurality of the pads located in a center portion of the semiconductor chip are arranged in a rectangular dot grid pattern, and a second plurality of the pads located in at least one of four corner portions of the semiconductor chip are arranged in a staggered dot pattern.
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