Invention Grant
US08456193B2 Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
有权
使用增强型门控Q扫描技术的集成电路泄漏功率降低
- Patent Title: Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
- Patent Title (中): 使用增强型门控Q扫描技术的集成电路泄漏功率降低
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Application No.: US12884482Application Date: 2010-09-17
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Publication No.: US08456193B2Publication Date: 2013-06-04
- Inventor: Rajamani Sethuram , Karim Arabi
- Applicant: Rajamani Sethuram , Karim Arabi
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Sam Talpalatsky; Nicholas J. Pauley; Joseph Agusta
- Main IPC: H03K19/173
- IPC: H03K19/173
Abstract:
Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
Public/Granted literature
- US20120068734A1 Integrated Circuit Leakage Power Reduction using Enhanced Gated-Q Scan Techniques Public/Granted day:2012-03-22
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