Invention Grant
- Patent Title: System and method for on-chip jitter and duty cycle measurement
- Patent Title (中): 用于片上抖动和占空比测量的系统和方法
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Application No.: US13446946Application Date: 2012-04-13
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Publication No.: US08456195B2Publication Date: 2013-06-04
- Inventor: Kallol Chatterjee , Anurag Tiwari
- Applicant: Kallol Chatterjee , Anurag Tiwari
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Hogan Lovells US LLP
- Priority: IN1614/DEL/2008 20080704
- Main IPC: H03K9/08
- IPC: H03K9/08

Abstract:
An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.
Public/Granted literature
- US20120218002A1 SYSTEM AND METHOD FOR ON-CHIP JITTER AND DUTY CYCLE MEASUREMENT Public/Granted day:2012-08-30
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