Invention Grant
- Patent Title: Delay locked loop with offset correction
- Patent Title (中): 具有偏移校正的延迟锁定环
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Application No.: US12961523Application Date: 2010-12-07
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Publication No.: US08456210B2Publication Date: 2013-06-04
- Inventor: Anant Shankar Kamath , SundaraSiva Rao Giduturi
- Applicant: Anant Shankar Kamath , SundaraSiva Rao Giduturi
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation.
Public/Granted literature
- US20120139595A1 DELAY LOCKED LOOP WITH OFFSET CORRECTION Public/Granted day:2012-06-07
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