Invention Grant
- Patent Title: NAND logic word line selection
- Patent Title (中): NAND逻辑字线选择
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Application No.: US12928949Application Date: 2010-12-22
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Publication No.: US08456946B2Publication Date: 2013-06-04
- Inventor: Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
- Applicant: Swaroop Ghosh , Dinesh Somasekhar , Balaji Srinivasan , Fatih Hamzaoglu
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G11C8/00
- IPC: G11C8/00
Abstract:
A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
Public/Granted literature
- US20120163114A1 NAND logic word line selection Public/Granted day:2012-06-28
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