Invention Grant
US08457919B2 Process for testing the resistance of an integrated circuit to a side channel analysis
有权
用于测试集成电路的电阻到侧面通道分析的过程
- Patent Title: Process for testing the resistance of an integrated circuit to a side channel analysis
- Patent Title (中): 用于测试集成电路的电阻到侧面通道分析的过程
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Application No.: US12750846Application Date: 2010-03-31
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Publication No.: US08457919B2Publication Date: 2013-06-04
- Inventor: Benoit Feix , Georges Gagnerot , Mylene Roussellet , Vincent Verneuil
- Applicant: Benoit Feix , Georges Gagnerot , Mylene Roussellet , Vincent Verneuil
- Applicant Address: FR Aix-en-Provence Cedex
- Assignee: Inside Secure
- Current Assignee: Inside Secure
- Current Assignee Address: FR Aix-en-Provence Cedex
- Agency: Panitch Schwarze Belisario & Nadel LLP
- Main IPC: G01R27/28
- IPC: G01R27/28

Abstract:
A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.
Public/Granted literature
- US20110246119A1 PROCESS FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO A SIDE CHANNEL ANALYSIS Public/Granted day:2011-10-06
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