A processor system according to an exemplary aspect of the present invention includes a first processor, a second processor, a control unit, a signal line group, and a selection circuit. The control unit switches an operation mode between a lock step mode for the first and second processors to execute the same instruction stream and a free step mode for the first and second processors to execute different instruction streams. The signal line group includes at least one signal line disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor. The signal line group is capable of transferring a storage state of the first memory circuit to the second memory circuit. The selection circuit is capable of switching a connection destination of the second memory circuit between the second processor and the signal line group.