Invention Grant
US08458532B2 Error handling mechanism for a tag memory within coherency control circuitry
有权
一致性控制电路内的标签存储器的错误处理机制
- Patent Title: Error handling mechanism for a tag memory within coherency control circuitry
- Patent Title (中): 一致性控制电路内的标签存储器的错误处理机制
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Application No.: US12926142Application Date: 2010-10-27
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Publication No.: US08458532B2Publication Date: 2013-06-04
- Inventor: Jocelyn Francois Orion Jaubert , Florent Begon , Melanie Emanuelle Lucie Teyssier
- Applicant: Jocelyn Francois Orion Jaubert , Florent Begon , Melanie Emanuelle Lucie Teyssier
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.
Public/Granted literature
- US20120110396A1 Error handling mechanism for a tag memory within coherency control circuitry Public/Granted day:2012-05-03
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