Invention Grant
US08458539B2 G-ODLAT on-die logic analyzer trigger with parallel vector finite state machine
失效
G-ODLAT在线逻辑分析仪触发并行向量有限状态机
- Patent Title: G-ODLAT on-die logic analyzer trigger with parallel vector finite state machine
- Patent Title (中): G-ODLAT在线逻辑分析仪触发并行向量有限状态机
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Application No.: US12823044Application Date: 2010-06-24
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Publication No.: US08458539B2Publication Date: 2013-06-04
- Inventor: Tsvika Kurts , Daniel Skaba , Michael Israeli , Itai Samoelov , Julius Mandelblat
- Applicant: Tsvika Kurts , Daniel Skaba , Michael Israeli , Itai Samoelov , Julius Mandelblat
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00 ; H04B3/46 ; H04B17/00 ; H04Q1/20

Abstract:
An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers.
Public/Granted literature
- US20110320893A1 G-ODLAT On-die Logic Analyzer Trigger with Parallel Vector Finite State Machine Public/Granted day:2011-12-29
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