Invention Grant
- Patent Title: Method and apparatus for testing of a memory with redundancy elements
- Patent Title (中): 用冗余元素测试存储器的方法和装置
-
Application No.: US12955354Application Date: 2010-11-29
-
Publication No.: US08458545B2Publication Date: 2013-06-04
- Inventor: Tanmoy Roy , Harsh Rawat , Swapnil Bahl , Amit Chhabra , Nitin Jain , Jatin Fultaria
- Applicant: Tanmoy Roy , Harsh Rawat , Swapnil Bahl , Amit Chhabra , Nitin Jain , Jatin Fultaria
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.
Public/Granted literature
- US20120137188A1 METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS Public/Granted day:2012-05-31
Information query
