Invention Grant
US08458560B2 Systems and methods for efficient parallel implementation of burst error correction codes 有权
用于高效并行执行突发纠错码的系统和方法

  • Patent Title: Systems and methods for efficient parallel implementation of burst error correction codes
  • Patent Title (中): 用于高效并行执行突发纠错码的系统和方法
  • Application No.: US12017629
    Application Date: 2008-01-22
  • Publication No.: US08458560B2
    Publication Date: 2013-06-04
  • Inventor: Jeffery T. Nichols
  • Applicant: Jeffery T. Nichols
  • Applicant Address: US MD Hanover
  • Assignee: Ciena Corporation
  • Current Assignee: Ciena Corporation
  • Current Assignee Address: US MD Hanover
  • Agency: Clements Bernard PLLC
  • Agent Christopher L. Bernard; Lawrence A. Baratta, Jr.
  • Main IPC: H03M13/00
  • IPC: H03M13/00
Systems and methods for efficient parallel implementation of burst error correction codes
Abstract:
The present invention provides systems and methods for an efficient, parallel implementation of burst error correction codes, such as the Fire code. The present invention includes a FEC decoder which is pipelined to simultaneously perform syndrome computation, error trapping and syndrome normalization, and error correction. The pipelined implementation can apply to shortened and full-length codes. Advantageously, the present invention yields a design which is approximately 1/20th the size of conventional parallel approaches.
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