Invention Grant
- Patent Title: Bios routine avoidance
- Patent Title (中): Bios常规避免
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Application No.: US11949317Application Date: 2007-12-03
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Publication No.: US08458726B2Publication Date: 2013-06-04
- Inventor: Vincent J. Zimmer , Jiewen Yao
- Applicant: Vincent J. Zimmer , Jiewen Yao
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F3/00
- IPC: G06F3/00

Abstract:
A method, computer readable medium, and device are disclosed. In one embodiment the method includes determining whether an entry exists in a firmware interface table to direct the processor to handle the event in a non-legacy mode. This is done after an event for a processor that triggers a legacy mode processor handling routine. The method also includes the processor handling the event in the non-legacy mode when the entry exists.
Public/Granted literature
- US20090144754A1 BIOS ROUTINE AVOIDANCE Public/Granted day:2009-06-04
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