A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gate formed through a second insulating film on a second side opposite to the first side; a first impurity implantation region (IIR1) in the substrate adjacent the first side gate; a second impurity implantation region (IIR2) formed in the substrate on a side of the second side gate; and a channel region between IIR1 and IIR2. The channel region includes a first region corresponding to a boundary between the CAL and the substrate; a select side region between the first region and IIR1; and an assist side region between the first region and IIR2. The select side region is longer than the assist side region.