Invention Grant
US08461651B2 ESD protection devices for SOI integrated circuit and manufacturing method thereof
失效
用于SOI集成电路的ESD保护器件及其制造方法
- Patent Title: ESD protection devices for SOI integrated circuit and manufacturing method thereof
- Patent Title (中): 用于SOI集成电路的ESD保护器件及其制造方法
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Application No.: US13002303Application Date: 2010-12-16
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Publication No.: US08461651B2Publication Date: 2013-06-11
- Inventor: Xiaolu Huang , Xing Wei , Xinhong Cheng , Jing Chen , Miao Zhang , Xi Wang
- Applicant: Xiaolu Huang , Xing Wei , Xinhong Cheng , Jing Chen , Miao Zhang , Xi Wang
- Applicant Address: CN Changning District Shanghai
- Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
- Current Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
- Current Assignee Address: CN Changning District Shanghai
- Agency: Global IP Services
- Agent Tianhua Gu
- Priority: CN201010532715 20101104
- International Application: PCT/CN2010/079847 WO 20101216
- International Announcement: WO2012/058840 WO 20120510
- Main IPC: H01L29/00
- IPC: H01L29/00
Abstract:
The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.
Public/Granted literature
- US20120112283A1 ESD PROTECTION DEVICES FOR SOI INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF Public/Granted day:2012-05-10
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