Invention Grant
US08462553B2 Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory
失效
单元阵列,用于高可缩放,字节可变的双晶体管FLOTOX EEPROM非易失性存储器
- Patent Title: Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory
- Patent Title (中): 单元阵列,用于高可缩放,字节可变的双晶体管FLOTOX EEPROM非易失性存储器
-
Application No.: US12930022Application Date: 2010-12-23
-
Publication No.: US08462553B2Publication Date: 2013-06-11
- Inventor: Peter Wung Lee , Fu-Chang Hsu
- Applicant: Peter Wung Lee , Fu-Chang Hsu
- Applicant Address: US CA San Jose
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
Two-transistor FLOTOX EEPROM cells are collected to form an alterable unit such as a byte. Each of the two-transistor FLOTOX EEPROM cells has a bit line connected to a drain of a select transistor of each of the two-transistor FLOTOX EEPROM cells and a source line placed in parallel with the bit line and connected to a source of a floating gate transistor of each of the two-transistor FLOTOX EEPROM cells. In a program operation, the bit lines are connected to a very large programming voltage level and the source lines are connected to a punch through inhibit voltage level. The punch through inhibit voltage level is approximately one half the very large programming voltage level. The lower drain-to-source voltage level permits the select transistor and the floating gate transistor to have smaller channel lengths and therefore a lower drain-to-source breakdown voltage.
Public/Granted literature
- US20110157974A1 Novel cell array for highly-scalable , byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory Public/Granted day:2011-06-30
Information query