Invention Grant
- Patent Title: Performing reliability analysis of signal wires
- Patent Title (中): 执行信号线的可靠性分析
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Application No.: US12944892Application Date: 2010-11-12
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Publication No.: US08463571B2Publication Date: 2013-06-11
- Inventor: Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
- Applicant: Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent Richard M. Kotulak, Esq.
- Main IPC: G06F19/00
- IPC: G06F19/00 ; G01R19/00

Abstract:
A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
Public/Granted literature
- US20120123725A1 PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES Public/Granted day:2012-05-17
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