Invention Grant
US08464032B2 Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit
有权
具有第一处理器的微处理器集成电路，其响应于集成电路的第二处理器的复位而输出调试信息
- Patent Title: Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit
- Patent Title (中): 具有第一处理器的微处理器集成电路，其响应于集成电路的第二处理器的复位而输出调试信息
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Application No.: US12748846Application Date: 2010-03-29
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Publication No.: US08464032B2Publication Date: 2013-06-11
- Inventor: G. Glenn Henry , Jui-Shuan Chen
- Applicant: G. Glenn Henry , Jui-Shuan Chen
- Applicant Address: TW New Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW New Taipei
- Agent E. Alan Davis; James W. Huffman
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F11/00
Abstract:
A microprocessor integrated circuit includes first and second processors. The first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor. The microprocessor integrated circuit also includes microcode. The second processor is configured to execute the microcode in response to a reset of the second processor. The microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor.
Public/Granted literature
- US20110010531A1 DEBUGGABLE MICROPROCESSOR Public/Granted day:2011-01-13
Information query
