Invention Grant
- Patent Title: Logic 1 and 0 formatter inputs for parallel scan paths
- Patent Title (中): 用于并行扫描路径的逻辑1和0格式化器输入
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Application No.: US13568533Application Date: 2012-08-07
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Publication No.: US08464116B2Publication Date: 2013-06-11
- Inventor: Lee D. Whetsel
- Applicant: Lee D. Whetsel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.
Public/Granted literature
- US20120304028A1 SCAN RESPONSE REUSE METHOD AND APPARATUS Public/Granted day:2012-11-29
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