Invention Grant
US08472268B2 Non-volatile semiconductor memory and simultaneous writing of data
有权
非易失性半导体存储器和数据同时写入
- Patent Title: Non-volatile semiconductor memory and simultaneous writing of data
- Patent Title (中): 非易失性半导体存储器和数据同时写入
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Application No.: US13428678Application Date: 2012-03-23
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Publication No.: US08472268B2Publication Date: 2013-06-25
- Inventor: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
- Applicant: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
- Applicant Address: JP Kawasaki-shi
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Kawasaki-shi
- Agency: Banner & Witcoff, Ltd.
- Priority: JP2000-63798 20000308; JP2000-323199 20001023
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range.
Public/Granted literature
- US20120182798A1 Non-Volatile Semiconductor Memory Public/Granted day:2012-07-19
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