A memory access apparatus is provided with a processor, an interface (I/F) circuit, and a memory control circuit. The processor is provided with an access-request generating circuit which issues a memory access request. The I/F circuit is provided with a flip-flop (F/F) circuit which holds the memory access request outputted from the processor in response to a clock signal. The memory control circuit is provided with an access processing circuit which executes an access process that complies with the memory access request held by the F/F circuit.