Invention Grant
- Patent Title: Method of manufacturing semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US13160653Application Date: 2011-06-15
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Publication No.: US08476113B2Publication Date: 2013-07-02
- Inventor: Bunshi Kuratomi , Fukumi Shimizu
- Applicant: Bunshi Kuratomi , Fukumi Shimizu
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Mattingly & Malur, PC
- Priority: JP2010-153973 20100706
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
When chip-scale molding system is employed for QFP, the number of semiconductor devices available from a leadframe decreases because cavities each requires a runner portion. This problem can be overcome by employing MAP system, but use of a laminate tape increases the production cost. In through mold system, each cavity needs an ejector pin, which however makes it difficult to place a support pillar. The present application provides a manufacturing method of a semiconductor device by filling, while sandwiching a leadframe between mold dies having a matrix-state cavity group in which cavity columns obtained by linking mold cavities in series via a through gate have been placed in rows, a sealing resin in the cavities. In this method, the matrix-state cavity group has, at the cavity corner portions thereof, a support pillar having a cross-section striding over all the cavities adjacent to the cavity corner portions when viewed planarly.
Public/Granted literature
- US20120009737A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2012-01-12
Information query
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