Invention Grant
- Patent Title: Reduction of etch microloading for through silicon vias
- Patent Title (中): 通过硅通孔减少蚀刻微加载
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Application No.: US13665164Application Date: 2012-10-31
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Publication No.: US08476116B2Publication Date: 2013-07-02
- Inventor: Hung-Pin Chang , Chen-Hua Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface.
Public/Granted literature
- US20130059443A1 REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS Public/Granted day:2013-03-07
Information query
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