Invention Grant
- Patent Title: Enhanced wafer test line structure
- Patent Title (中): 增强晶圆测试线结构
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Application No.: US13246536Application Date: 2011-09-27
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Publication No.: US08476629B2Publication Date: 2013-07-02
- Inventor: Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
- Applicant: Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
- Applicant Address: TW Hsin-Chun
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chun
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L27/12
Abstract:
A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.
Public/Granted literature
- US20130075725A1 ENHANCED WAFER TEST LINE STRUCTURE Public/Granted day:2013-03-28
Information query
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