Invention Grant
- Patent Title: Semiconductor memory device
- Patent Title (中): 半导体存储器件
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Application No.: US12745133Application Date: 2008-09-08
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Publication No.: US08476641B2Publication Date: 2013-07-02
- Inventor: Yoshiyuki Suda , Yutaka Ota
- Applicant: Yoshiyuki Suda , Yutaka Ota
- Applicant Address: JP Fuchu-shi
- Assignee: National University Corporation Tokyo University of Agriculture and Technology
- Current Assignee: National University Corporation Tokyo University of Agriculture and Technology
- Current Assignee Address: JP Fuchu-shi
- Agency: Morrison & Foerster LLP
- Priority: JP2007-310662 20071130
- International Application: PCT/JP2008/066500 WO 20080908
- International Announcement: WO2009/069365 WO 20090604
- Main IPC: H01L29/24
- IPC: H01L29/24

Abstract:
A switching resistance RAM that is highly integrated as well as reduced in a read-out time is realized. There is formed an NPN type bipolar transistor BT composed of a collector layer made of an N-well 11, a base layer made of a P+ type Si layer 12A formed in a surface of the N-well 11, and an emitter layer made of an N+ type Si layer 15 formed in a surface of the P+ type Si layer 12A. Also, there are formed a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1-BL4 intersecting with the word line WL0. Also, there are formed a plurality of switching layers 14 formed on a surface of the P+ type Si layer 12A, each being electrically connected to corresponding each of the bit lines and switching between an ON state and an OFF state and an electric potential fixing line 19A to fix the P+ type Si layer 12A at a predetermined electric potential.
Public/Granted literature
- US20100308341A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2010-12-09
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